Student at GLAU-GLA University
Feb-2016 to Jul-2016
This paper primarily deals with the construction of Arithmetic Logic Unit (ALU) using Hardware Description Language (HDL). The design was implemented using VHDL Xilinx Synthesis tool ISE 14.2 and targeted for Spartan device. ALU was designed to perform arithmetic operations such as addition and subtraction using 8-bit fast adder, logical operations such as AND, OR, XOR and NOT operations, 1’s and 2’s complement operations and compare. ALU consist of two input registers to hold the data during operation, one output register to hold the result of operation, 8-bit fast adder with 2’s complement circuit to perform subtraction and logic gates to perform logical operation. The maximum propagation delay is 13.588ns and power dissipation is 38mW. The ALU was designed for controller used in network interface card.