K Bharath Kalyan - VLSI, Aptitude - Bangalore

K Bharath Kalyan
Vlsi Fresher
Bangalore, Karnataka, India
VLSI Aptitude ASIC Physical Design Static Timing Analysis
Other

About K Bharath Kalyan

K Bharath Kalyan is based in Bangalore, India. K studied Bachelor of Engineering or Technology (ECE ENTC-Electronics and Tele-Communication Engineering) (2012-2016). On Youth4work, K has taken skill tests in VLSI (rank 187 of 11,946, top 2%), Aptitude (rank 74,818 of 3,606,048, top 3%) and ASIC Physical Design (rank 158 of 1,128, top 15%). K also lists talents in Static Timing Analysis.

Talents

VLSI

... among ... users in Bangalore

187

among 11946 users worldwide

58.23

percentile among worldwide users
ASIC Physical Design

... among ... users in Bangalore

158

among 1128 users worldwide

22.89

percentile among worldwide users
Aptitude

... among ... users in Bangalore

74818

among 3606048 users worldwide

45.49

percentile among worldwide users

Complete Talent Profile »

Professional Path

VLSI PGD

ITRI Internships

Sep-2016 To Mar-2017 6 months

» 3 Projects

Physical Design & Verification of DTMF Chip

Jan-2017 to Mar-2017

Objective : To do the floor planning, Power planning, placement, CTS,
Routing, Design signoff, Generating GDS II.
Tools : SOC Encounter, RTL Compiler
Gate count / Area : 6K
No. of Clocks : 2
Macro count : 4
Frequency : 125 MHz
Utilization : 70.1 %
Technology / Layers : TSMC 0.09 microns / 6 Metal Layers
Role:
Floor Plan, Power Plan, Placement, Trial Route.
Timing Analysis, CTC, Detail Routing.
To observe the relation between core utilization, wire length and number of metal layers.

Schematic Design & Custom Layout & Verification

Nov-2016 to Dec-2016

Objective : Schematic Design, Layout Design & Verification (DRC, LVS, ERC)
of all the Gates, Current Mirror, Differential Amplifier, OP-AMP.
Tools : Virtuoso Schematic Editor, Spectre, Virtuoso Layout Editor, Assura
Technology / Layers : gpdk180 / 4 Metal Layers
Role:
Schematic Design on Virtuoso Schematic Editor.
Circuit Simulation on Spectre Tool.
Layout Design on Virtuoso Layout Editor.
Physical Verification, DRC, LVS, ERC on Assura.
Simulation with Parasitic Extraction on Spectre.

Schematic Design & Custom Layout & Verification of PLL

Oct-2016 to Nov-2016

Objective : Schematic Design, Layout Design & Verification (DRC, LVS, ERC)
of PFD, Charge Pump, VCO
Tools : Virtuoso Schematic Editor, Spectre, Virtuoso Layout Editor, Assura
Technology / Layers : gpdk180 / 4 Metal Layers
Role:
Schematic Design on Virtuoso Schematic Editor.
Circuit Simulation on Spectre Tool.
Layout Design on Virtuoso Layout Editor.
Physical Verification, DRC, LVS, ERC on Assura.
Simulation with Parasitic Extraction on Spectre.

Qualifications

Other

Bachelor of Engineering or Technology ECE ENTC-Electronics and Tele-Communication Engineering

2012-2016

63%

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