I have taken a Netlist. Now I am doing synthesis of this Netlist using two different technology nodes. All the other parameters are same. During synthesis I am generating timing report after GENERIC stage. As far as I know this stage is technology independent. But generated timing report has different delays for both the technology node. How? From where does these delays are taken by tool? If they are taken from tool library than which tool library and why delays are different?
Didn't get the answer.
Contact people of Talent-Vlsi directly by clicking here