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Abhijeet Sureshrao Shinde

Fresher(2017) - Looking For Opportunities In Vlsi Domain.
  • Bangalore, Karnataka, India
  • ASIC Physical Design, Logic Design, Static Timing Analysis
Profile Snapshot
Abhijeet is based out of Bangalore & has studied VLSI Design and Embedded Systems, ME MTech-Master of Engineering or Technology from Year 2015-2017 in VIT University, Deemed University.
Abhijeet Sureshrao Shinde is Skilled in ASIC Physical Design, Logic Design, Static Timing Analysis and other talents.
My Story
Looking For Opportunities in Physical Design,STA, ASIC/FPGA Design ,Layout Design and Memory Design.
Qualifications
Master of Engineering or Technology
VIT UniversityDeemed University
2015-2017

Bachelor of Engineering or Technology
M I T PunePUNE UNIVERSITY
2011-2014 | Score 68%