Akshay G Bhat - BE BTech, Ramaiah Institute of Technology - Bangalore

Akshay G Bhat
Akshay G Bhat
Bangalore, Karnataka, India
Aptitude Financial Management Telecommunications
RIT-Ramaiah Institute of Technology

About Akshay G Bhat

Akshay G Bhat is based in Bangalore, India. Akshay studied Bachelor of Engineering or Technology (ECE-Electronics and Computer Engineering) at Ramaiah Institute of Technology (2012-2016). On Youth4work, Akshay has taken skill tests in Aptitude (rank 1,594 of 3,606,048, top 1%), Financial Management (rank 32 of 22,840, top 1%) and Telecommunications (rank 53 of 19,402, top 1%). Akshay also lists talents in Math and Science Tutor, Electronics Engineering, Network Engineer and Statistics.

Talents

Quantitative Analysis

... among ... users in Bangalore

…

among … users worldwide

45.46

percentile among worldwide users
Social Media

... among ... users in Bangalore

…

among … users worldwide

48.04

percentile among worldwide users
Telecommunications

... among ... users in Bangalore

53

among 19402 users worldwide

94.81

percentile among worldwide users
VLSI

... among ... users in Bangalore

…

among … users worldwide

72.29

percentile among worldwide users

Complete Talent Profile »

Professional Path

INTERN

Robert Bosch Internships

Jan-2016 To Apr-2016 3 months

» 1 Project

STT MTJ CMOS Hybrid 5 bit SAR ADC

Student at RIT-Ramaiah Institute of Technology

Nov-2015 to Mar-2016

Reducing power consumption in data converters is a major challenge. This project proposes the use of STT-MTJ based comparator in a 5-bit Successive approximation analog to digital converter. The proposed system uses a hybrid design where both CMOS and STT-MTJ are used in the analog to digital converter. The use of this newer device in the traditional successive approximation adc was found to reduce the power consumption of the analog to digital converter without compromising on the speed or performance of the circuit. Experiments were designed and conducted to quantify the performance the circuit and also compare it with existing technologies. These simulations showed that the proposed system consumed 2mW, when the supply in both the cases is 1.8V, which is less power compared to other traditional designs. The power consumed by the proposed system is considerably lower than most counterpart designs done in the CMOS technology. The proposed system consumes an average power of 3.26mW wh

Qualifications

Ramaiah Institute of Technology

Bachelor of Engineering or Technology Electronics and Computer Engineering

2012-2016

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