Arshabha Arya

Arshabha Arya
B.Tech In Electronics And Communications Engineering (Ece)
Delhi, Delhi, India
Microprocessor Embedded Systems Aptitude Telecommunications
GLAU-GLA University

About Arshabha Arya

Arshabha Arya works as Web Developer at - and is based in Delhi, India. Arshabha studied Bachelor of Engineering or Technology (ECE ENTC-Electronics and Tele-Communication Engineering) at GLA University (2013-2017). On Youth4work, Arshabha has taken skill tests in Microprocessor (rank 27 of 11,927, top 1%), Embedded Systems (rank 27 of 27,309, top 1%) and Aptitude (rank 1,342 of 3,606,048, top 1%). Arshabha also lists talents in VLSI, HTML, CSS and Network Engineer.

Talents

Telecommunications

... among ... users in Delhi

26

among 19402 users worldwide

98.54

percentile among worldwide users
VLSI

... among ... users in Delhi

…

among … users worldwide

89.61

percentile among worldwide users
Embedded Systems

... among ... users in Delhi

27

among 27309 users worldwide

99.44

percentile among worldwide users
Network Engineer

... among ... users in Delhi

…

among … users worldwide

42.5

percentile among worldwide users

Complete Talent Profile »

Professional Path

Web Developer

- Full Time

May-2017 To present 9 years 4 months

» 2 Projects

An Ultra-Wideband CMOS Low Noise Amplifier using cascade and cascode topology for 3-5GHz Frequency

Student at GLAU-GLA University

Jun-2016 to Jun-2017

This project deals with the design of a low noise amplifier for ultra wideband (UWB) frequency range from 3-5 GHz considered various parameters which affects its performance and efficiency of subsequent devices that follows. It helps to choose the optimum parameter and choice of different topologies and techniques. This will lead to better gain, noise figure, power consumption etc. The report consists of all the information about the parameter involved the design low noise amplifier. Also, I have specified the values and conditions under which each of the components works. All the parameters value has been tabulated and appropriate graphs have been shown. In this project, I have simulated the proposed circuits on Advanced Design System (ADS) tool and achieved better values for gain and noise figure with low power consumption. The scope of our project is to: Minimum noise figure and enhance gain.

VHDL Implementation of 8-Bit ALU

Student at GLAU-GLA University

Feb-2016 to Jul-2016

This paper primarily deals with the construction of Arithmetic Logic Unit (ALU) using Hardware Description Language (HDL). The design was implemented using VHDL Xilinx Synthesis tool ISE 14.2 and targeted for Spartan device. ALU was designed to perform arithmetic operations such as addition and subtraction using 8-bit fast adder, logical operations such as AND, OR, XOR and NOT operations, 1’s and 2’s complement operations and compare. ALU consist of two input registers to hold the data during operation, one output register to hold the result of operation, 8-bit fast adder with 2’s complement circuit to perform subtraction and logic gates to perform logical operation. The maximum propagation delay is 13.588ns and power dissipation is 38mW. The ALU was designed for controller used in network interface card.

Qualifications

GLA University

Bachelor of Engineering or Technology ECE ENTC-Electronics and Tele-Communication Engineering

2013-2017

70%

My Work

Portfolio June, 21 2021

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Extra-Curricular Interests

1. International Conference on “UWB Active Antenna System”. 2. National Workshop on “LabVIEW”. 3. National Workshop on “Advancement in Mobile Communication”. 4. Work as a Volunteer in “IEEE International Conference CCIS”.

My Story

I am good Team Player."works enthusiastically. I have enough motivation for myself and my department. I love what I do, and it’s contagious.”

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