Kiruthiga K | Youth4work

Kiruthiga K
Technology Vicissitude
Chennai, Tamil Nadu, India
Perl Scripting Aptitude Communication Skills
VIT-Vellore Institute of Technology

Profile Snapshot

Kiruthiga is based out of Chennai & has studied VLSI Design and Embedded Systems, ME MTech-Master of Engineering or Technology from Year 2018-2020 in VIT-Vellore Institute of Technology, VIT University.

Kiruthiga K is Skilled in Perl Scripting, Aptitude, Communication Skills and other talents.

Profile Snapshot

Kiruthiga K is Skilled in Perl Scripting, Aptitude, Communication Skills and other talents.

Talents

C Language

... among 0 users in Chennai

…

among 0 users worldwide

41.38

percentile among worldwide users
Communication Skills

... among 0 users in Chennai

…

among 0 users worldwide

45.69

percentile among worldwide users
Internet

... among 0 users in Chennai

…

among 0 users worldwide
Perl Scripting

... among 0 users in Chennai

…

among 0 users worldwide

95.54

percentile among worldwide users

Complete Talent Profile »

Professional Path

Project Engineer -L1

Wipro Limited Full Time

Oct-2017 To Jul-2018 9 months

» 2 Projects

ASIC Implementation of Low Power FFT Processor using Clock-Gating Techniques

Jan-2019 to Mar-2019

We focused on reducing power in radix-2 based FFT processor using clock-gating techniques. The FFT processor is implemented with single precision floating point units using pipeline architecture. With increased demands for low power, clock gating technique becomes necessary. It is the preferred techniques in ASIC designs, to the field of FPGA based system. The design is realized using ASIC pre-synthesis implementation flow by applying respective power reduction techniques. Finally, comparison of power is made between the FFT processor with and without clock- gating techniques

Low Power Dynamic Logic schmitt Trigger using FinFET Technology

Aug-2018 to Nov-2018

This project involves design and implementation of low power dynamic logic-based Schmitt trigger using 32nm FinFET technology. The performance parameters such as slew rate, output noise voltage, leakage power, power dissipation is calculated in both CMOS and FinFET technique and compared to determine the performance of the circuit.. The circuit is simulated in Cadence virtuoso tool version 6.1.

Qualifications