Savan Mirajkar - ASIC Verification/Design Engineer - Bangalore

Savan Mirajkar
Asic Verification/Design Engineer
Bangalore, Karnataka, India
VLSI C Plus Plus Logic Design Verilog
AIEMS-Amruta Institute of Engineering and Management Sciences

About Savan Mirajkar

Savan Mirajkar is based in Bangalore, India. Savan studied Bachelor of Engineering or Technology (ECE ENTC-Electronics and Tele-Communication Engineering) at Amruta Institute of Engineering and Management Sciences (2010-2014). On Youth4work, Savan has taken skill tests in VLSI (rank 1,555 of 11,946, top 14%) and C Plus Plus (rank 38,985 of 86,076, top 46%). Savan also lists talents in Logic Design, Verilog, Unix and Linux and Training Skills.

Talents

Query Optimization

... among ... users in Bangalore

…

among … users worldwide
Training Skills

... among ... users in Bangalore

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among … users worldwide
VLSI

... among ... users in Bangalore

1555

among 11946 users worldwide

67.09

percentile among worldwide users
C Plus Plus

... among ... users in Bangalore

38985

among 86076 users worldwide

25.02

percentile among worldwide users

Complete Talent Profile »

Professional Path

Trainee-(ASIC Design/Verification Engineer)

RV VLSI Design Center Internships

Jul-2014 To Jan-2015 6 months

My experience includes writing and outlining test and coverage plans and I am familiar with ASIC verification field and debugging. My experience also includes developing test infrastructures and I have extensive knowledge of programming, logic design concepts, transistor theory and stimulators.

» 4 Projects

Verification of Mini UART using System-Verilog and UVM.

Dec-2014 to Jan-2015

Development of verification plan and System-Verilog and UVM Testbench Architecture for Mini UART Subsystem incorporated with a Micro UART core and a dedicated synchronous Microprocessor bus interface. Verification of functionality with randomized and directed test cases leading to maximum functional coverage for UART protocol.

Verification of Synchronous FIFO using System verilog and UVM.

Nov-2014 to Dec-2014

Verification of synchronous FIFO using SystemVerilog and UVM methodology with maximum functional coverage. Development of different test sequences for write, read, simultaneous write/read operations. In UVM implementation of TLM in the testbench to have connections between the verification components. Providing best frame-work for coverage driven verification.

Verification of Single port RAM using System-verilog.

Oct-2014 to Nov-2014

This project was aimed to verify a simple RAM to get introduced to verification architecture. Test plan creation from Design Specification, Self-Checking Testbench,
Code Coverage, Functional Coverage, Constrained Randomization, Regressions, Random and Directed Testing Methodology and Corner Cases. Development of different test sequences were done and 100% functional coverage was achieved.

Implementation of vertical mode controller of an aircraft, using aurdino uno board and flight gear flight simulator.

Student at AIEMS-Amruta Institute of Engineering and Management Sciences

Feb-2014 to Apr-2014

This project aims to design a system that controls vertical position of an aircraft. This involves pitch and altitude hold. In modern aircrafts, the autopilot system is more expensive as its components and design are very accurate and stable. This project involves the study of system using less expensive and open source hardware ARDUINO board and software such as MATLAB. To visualize the response of FLIGHTGEAR flight simulator has been used. Interfacing flight simulator with Matlab helps us to better understand the behavior of the autopilot system based on our inputs. This project also provides good hands-on on control system.

Qualifications

Amruta Institute of Engineering and Management Sciences

Bachelor of Engineering or Technology ECE ENTC-Electronics and Tele-Communication Engineering

2010-2014

My Story

I am looking for the position of ASIC Verification Engineer or RTL Design Engineer in VLSI field

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